| Low-power level shifter for multi-supply voltage designs M Lanuzza, P Corsonello, S Perri IEEE Transactions on Circuits and Systems II: Express Briefs 59 (12), 922-926, 2012 | 141 | 2012 |
| Skyrmion based microwave detectors and harvesting MC G Finocchio, M Ricci, R Tomasello, A Giordano, M Lanuzza, V Puliafito, P ... Applied Physics Letters 107 (26), 262401, 2015 | 123 | 2015 |
| Fast and wide range voltage conversion in multisupply voltage designs M Lanuzza, P Corsonello, S Perri IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 388-391, 2014 | 112 | 2014 |
| An ultralow-voltage energy-efficient level shifter M Lanuzza, F Crupi, S Rao, R De Rose, S Strangio, G Iannaccone IEEE Transactions on Circuits and Systems II: Express Briefs 64 (1), 61-65, 2016 | 105 | 2016 |
| Digital and analog TFET circuits: Design and benchmark S Strangio, F Settino, P Palestri, M Lanuzza, F Crupi, D Esseni, L Selmi Solid-State Electronics 146, 50-65, 2018 | 76 | 2018 |
| Mixed tunnel-FET/MOSFET level shifters: A new proposal to extend the tunnel-FET application domain M Lanuzza, S Strangio, F Crupi, P Palestri, D Esseni IEEE Transactions on Electron Devices 62 (12), 3973-3979, 2015 | 74 | 2015 |
| Understanding the potential and limitations of tunnel FETs for low-voltage analog/mixed-signal circuits F Settino, M Lanuzza, S Strangio, F Crupi, P Palestri, D Esseni, L Selmi IEEE Transactions on Electron Devices 64 (6), 2736-2743, 2017 | 67 | 2017 |
| A high-performance fully reconfigurable FPGA-based 2D convolution processor S Perri, M Lanuzza, P Corsonello, G Cocorullo Microprocessors and Microsystems 29 (8-9), 381-391, 2005 | 65 | 2005 |
| Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates P Corsonello, M Lanuzza, S Perri International journal of circuit theory and applications 42 (1), 65-70, 2014 | 62 | 2014 |
| Assessment of InAs/AlGaSb tunnel-FET virtual technology platform for low-power digital circuits S Strangio, P Palestri, M Lanuzza, F Crupi, D Esseni, L Selmi IEEE Transactions on Electron Devices 63 (7), 2749-2756, 2016 | 57 | 2016 |
| A variation-aware timing modeling approach for write operation in hybrid CMOS/STT-MTJ circuits R De Rose, M Lanuzza, F Crupi, G Siracusano, R Tomasello, G Finocchio, ... IEEE Transactions on Circuits and Systems I: Regular Papers 65 (3), 1086-1095, 2017 | 51 | 2017 |
| Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI R Taco, I Levi, M Lanuzza, A Fish Solid-State Electronics 117, 185-192, 2016 | 51 | 2016 |
| A new reconfigurable coarse-grain architecture for multimedia applications M Lanuzza, S Perri, P Corsonello, M Margala Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 119-126, 2007 | 51 | 2007 |
| A compact model with spin-polarization asymmetry for nanoscaled perpendicular MTJs R De Rose, M Lanuzza, M d’Aquino, G Carangelo, G Finocchio, F Crupi, ... IEEE Transactions on Electron Devices 64 (10), 4346-4353, 2017 | 50 | 2017 |
| Low-power split-path data-driven dynamic logic F Frustaci, M Lanuzza, P Zicari, S Perri, P Corsonello IET circuits, devices & systems 3 (6), 303-312, 2009 | 50 | 2009 |
| Low bit rate image compression core for onboard space applications P Corsonello, S Perri, G Staino, M Lanuzza, G Cocorullo IEEE transactions on circuits and systems for video technology 16 (1), 114-128, 2005 | 45 | 2005 |
| Spin–orbit torque based physical unclonable function G Finocchio, T Moriyama, R De Rose, G Siracusano, M Lanuzza, ... Journal of Applied Physics 128 (3), 2020 | 44 | 2020 |
| Variability-aware analysis of hybrid MTJ/CMOS circuits by a micromagnetic-based simulation framework R De Rose, M Lanuzza, F Crupi, G Siracusano, R Tomasello, G Finocchio, ... IEEE Transactions on Nanotechnology 16 (2), 160-168, 2016 | 42 | 2016 |
| Opto‐electrical modelling and optimization study of a novel IBC c‐Si solar cell P Procel, A Ingenito, R De Rose, S Pierro, F Crupi, M Lanuzza, ... Progress in Photovoltaics: Research and Applications 25 (6), 452-469, 2017 | 41 | 2017 |
| Designing high-speed adders in power-constrained environments F Frustaci, M Lanuzza, P Zicari, S Perri, P Corsonello IEEE Transactions on Circuits and Systems II: Express Briefs 56 (2), 172-176, 2009 | 41 | 2009 |
Felice CrupiDIMES, Università della Calabria在 unical.it 的电子邮件经过验证
