Self-Heating Mapping of the Experimental Device and Its Optimization in Advance Sub-5nm Node Junctionless Multi-Nanowire FETs N Kumar, S Pali, A Gupta, P Singh IEEE Transactions on Device and Materials Reliability, 2023 | 4 | 2023 |
Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability S Pali, A Gupta IEEE Access 9, 155370-155379, 2021 | 4 | 2021 |
Drain Extended MOS Body Region Engineering for Switching Reliability Under Unclamped Inductive Load Conditions S Pali, N Kumar, A Gupta IEEE Transactions on Device and Materials Reliability 23 (1), 134-141, 2023 | 2 | 2023 |
Drain-extended MOS design using High-k dielectric to control off-state BTBT with enhanced switching performance S Pali, PK Kaushik, A Gupta Engineering Research Express 4 (3), 035011, 2022 | 2 | 2022 |
High-k field plate DeNMOS design for enhanced performance and electrothermal SOA in switching applications S Pali, A Gupta Microelectronics Journal 130, 105615, 2022 | 1 | 2022 |
Physical Insights on Current Dynamics of RESURF DeMOS Designed for High-Frequency CMOS Level Shifter Application S Pali, A Gupta IETE Technical Review 40 (5), 611-620, 2023 | | 2023 |
P-type trench gate based drain-extended N-type MOS design for high unclamped inductive switching reliability S Pali, N Kumar, A Gupta Microelectronics Journal 139, 105894, 2023 | | 2023 |
Design and analysis of drain-extended MOS (DeMOS) for improved switching performance and electrothermal switching reliability S Pali IIT Delhi, 2023 | | 2023 |
Optimization of Drain Extended MOS Devices for Reliability in High Switching applications S Pali, A Gupta 2020 5th IEEE International Conference on Emerging Electronics (ICEE), 1-4, 2020 | | 2020 |
Drain-extended NMOS(DeNMOS) and a method thereof to optimize parasitic BJT trigger voltage and self-heating induced thermal runaway IN Patent App. 202,211,037,982, 0 | | |