An all-digital phase-locked loop for high-speed clock generation CC Chung, CY Lee IEEE Journal of solid-state circuits 38 (2), 347-351, 2003 | 307 | 2003 |
A portable digitally controlled oscillator using novel varactors PL Chen, CC Chung, CY Lee IEEE Transactions on Circuits and Systems II: Express Briefs 52 (5), 233-237, 2005 | 144 | 2005 |
An ultra-low-power and portable digitally controlled oscillator for SoC applications D Sheng, CC Chung, CY Lee IEEE Transactions on Circuits and Systems II: Express Briefs 54 (11), 954-958, 2007 | 113 | 2007 |
An autocalibrated all-digital temperature sensor for on-chip thermal monitoring CC Chung, CR Yang IEEE Transactions on Circuits and Systems II: Express Briefs 58 (2), 105-109, 2011 | 97 | 2011 |
A new DLL-based approach for all-digital multiphase clock generation CC Chung, CY Lee IEEE Journal of Solid-State Circuits 39 (3), 469-475, 2004 | 97 | 2004 |
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications PL Chen, CC Chung, JN Yang, CY Lee IEEE Journal of Solid-State Circuits 41 (6), 1275-1285, 2006 | 73 | 2006 |
A 480Mb/s LDPC-COFDM-based UWB baseband transceiver HY Liu, CC Lin, YW Lin, CC Chung, KL Lin, WC Chang, LH Chen, ... ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 56 | 2005 |
Partial parity cache and data cache management method to improve the performance of an SSD-based RAID CC Chung, HH Hsu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (7 …, 2013 | 51 | 2013 |
A fast phase tracking ADPLL for video pixel clock generation in 65 nm CMOS technology CC Chung, CY Ko IEEE Journal of Solid-state circuits 46 (10), 2300-2311, 2011 | 51 | 2011 |
An all-digital phase-locked loop with high-resolution for SoC applications D Sheng, CC Chung, CY Lee 2006 International Symposium on VLSI Design, Automation and Test, 1-4, 2006 | 45 | 2006 |
A 0.52/1 V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling CC Chung, WS Su, CK Lo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (1), 408-412, 2015 | 44 | 2015 |
A low-power DCO using interlaced hysteresis delay cells CY Yu, CC Chung, CJ Yu, CY Lee IEEE Transactions on Circuits and Systems II: Express Briefs 59 (10), 673-677, 2012 | 34 | 2012 |
An all-digital delay-locked loop for DDR SDRAM controller applications CC Chung, PL Chen, CY Lee 2006 International Symposium on VLSI Design, Automation and Test, 1-4, 2006 | 27 | 2006 |
A wide-range low-cost all-digital duty-cycle corrector CC Chung, D Sheng, CJ Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (11 …, 2014 | 24 | 2014 |
High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology CC Chung, D Sheng, SE Shen IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5 …, 2013 | 24 | 2013 |
A wide-range all-digital delay-locked loop in 65nm CMOS technology CC Chung, CL Chang Proceedings of 2010 International Symposium on VLSI Design, Automation and …, 2010 | 24 | 2010 |
A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications D Sheng, CC Chung, CY Lee APCCAS 2006-2006 IEEE Asia Pacific Conference on Circuits and Systems, 105-108, 2006 | 23 | 2006 |
Built-in self-calibration circuit for monotonic digitally controlled oscillator design in 65-nm CMOS technology CC Chung, CY Ko, SE Shen IEEE Transactions on Circuits and Systems II: Express Briefs 58 (3), 149-153, 2011 | 22 | 2011 |
A monotonic and low-power digitally controlled oscillator with portability for SoC applications D Sheng, JC Lan 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 20 | 2011 |
A low-power and portable spread spectrum clock generator for SoC applications D Sheng, CC Chung, CY Lee IEEE transactions on very large scale integration (VLSI) systems 19 (6 …, 2010 | 20 | 2010 |