| Improvement in reliability of tunneling field-effect transistor with pnin structure W Cao, CJ Yao, GF Jiao, D Huang, HY Yu, MF Li IEEE transactions on electron devices 58 (7), 2122-2126, 2011 | 135 | 2011 |
| Novel Vertical Channel-All-Around (CAA) In-Ga-Zn-O FET for 2T0C-DRAM With High Density Beyond 4F2 by Monolithic Stacking X Duan, K Huang, J Feng, J Niu, H Qin, S Yin, G Jiao, D Leonelli, X Zhao, ... IEEE Transactions on Electron Devices 69 (4), 2196-2202, 2022 | 84 | 2022 |
| Effect of interface traps and oxide charge on drain current degradation in tunneling field-effect transistors XY Huang, GF Jiao, W Cao, D Huang, HY Yu, ZX Chen, N Singh, GQ Lo, ... IEEE Electron Device Letters 31 (8), 779-781, 2010 | 66 | 2010 |
| New degradation mechanisms and reliability performance in tunneling field effect transistors GF Jiao, ZX Chen, HY Yu, XY Huang, DM Huang, N Singh, GQ Lo, ... 2009 IEEE international electron devices meeting (IEDM), 1-4, 2009 | 55 | 2009 |
| Investigation of hot carrier degradation in bulk FinFET EA Chung, KJ Nam, T Nakanishi, S Park, H Yang, T Kauerauf, G Jiao, ... 2017 IEEE International Reliability Physics Symposium (IRPS), XT-6.1-XT-6.4, 2017 | 29 | 2017 |
| Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device E Chung, JD Choi, T Nakanishi, Y Kim, G Nam, DK Lee, G Jiao US Patent 9,564,435, 2017 | 28 | 2017 |
| Experimental Investigation of Border Trap Generation in InGaAs nMOSFETs WithGate Dielectric Under PBTI Stress G Jiao, C Yao, Y Xuan, D Huang, DY Peide, MF Li IEEE transactions on electron devices 59 (6), 1661-1667, 2012 | 27 | 2012 |
| Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for … K Huang, X Duan, J Feng, Y Sun, C Lu, C Chen, G Jiao, X Lin, J Shao, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 24 | 2022 |
| Positive bias temperature instability degradation of InGaAs n-MOSFETs with Al2O3gate dielectric GF Jiao, W Cao, Y Xuan, DM Huang, PD Ye, MF Li 2011 International Electron Devices Meeting, 27.1. 1-27.1. 4, 2011 | 23 | 2011 |
| Low frequency noise in tunneling field effect transistors ST Bu, DM Huang, GF Jiao, HY Yu, MF Li Solid-State Electronics 137, 95-101, 2017 | 19 | 2017 |
| Reliability of high-mobility InGaAs channel n-MOSFETs under BTI stress MF Li, G Jiao, Y Hu, Y Xuan, D Huang, DY Peide IEEE Transactions on Device and Materials Reliability 13 (4), 515-523, 2013 | 17 | 2013 |
| Experimental studies of reliability issues in tunneling field-effect transistors GF Jiao, ZX Chen, HY Yu, XY Huang, DM Huang, N Singh, GQ Lo, ... IEEE Electron Device Letters 31 (5), 396-398, 2010 | 16 | 2010 |
| Investigation of asymmetric characteristics of novel vertical channel-all-around (CAA) In-Ga-Zn-O field effect transistors Q Chen, L Wang, X Duan, J Guo, Z Wang, K Huang, J Feng, Y Sun, G Jiao, ... IEEE Electron Device Letters 43 (6), 894-897, 2022 | 15 | 2022 |
| Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability J Guo, Y Sun, L Wang, X Duan, K Huang, Z Wang, J Feng, Q Chen, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 12 | 2022 |
| PBTI-induced random timing jitter in circuit-speed random logic J Lu, G Jiao, C Vaz, JP Campbell, JT Ryan, KP Cheung, G Bersuker, ... IEEE Transactions on Electron Devices 61 (11), 3613-3618, 2014 | 12 | 2014 |
| Extraction of Channel Electron Effective Mobility in InGaAs/AlOn-FinFETs Y Hu, S Li, G Jiao, YQ Wu, D Huang, DY Peide, MF Li IEEE transactions on nanotechnology 12 (5), 806-809, 2013 | 12 | 2013 |
| Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB G Jiao, M Toledano-Luque, KJ Nam, N Toshiro, SH Lee, JS Kim, ... 2016 IEEE International Electron Devices Meeting (IEDM), 31.2. 1-31.2. 4, 2016 | 8 | 2016 |
| Device-level PBTI-induced timing jitter increase in circuit-speed random logic operation JW Lu, C Vaz, JP Campbell, JT Ryan, KP Cheung, GF Jiao, G Bersuker, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 4 | 2014 |
| Circuit speed timing jitter increase in random logic operation after NBTI stress GF Jiao, JW Lu, JP Campbell, JT Ryan, KP Cheung, CD Young, ... 2014 IEEE International Reliability Physics Symposium, 6B. 1.1-6B. 1.4, 2014 | 3 | 2014 |
| Investigation of tunneling field effect transistor reliability GF Jiao, XY Huang, ZX Chen, W Cao, DM Huang, HY Yu, N Singh, GQ Lo, ... 2010 10th IEEE International Conference on Solid-State and Integrated …, 2010 | 3 | 2010 |
