| Through-silicon hole interposers for 3-D IC integration JH Lau, CK Lee, CJ Zhan, ST Wu, YL Chao, MJ Dai, RM Tain, HC Chien, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 4 (9 …, 2014 | 51 | 2014 |
| Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration L Li, P Su, J Xue, M Brillhart, J Lau, PJ Tzeng, CK Lee, CJ Zhan, MJ Dai, ... 2012 IEEE 62nd electronic components and technology conference, 1040-1046, 2012 | 50 | 2012 |
| Energy release rate estimation for through silicon vias in 3-D IC integration MC Hsieh, ST Wu, CJ Wu, JH Lau IEEE Transactions on Components, Packaging and Manufacturing Technology 4 (1 …, 2013 | 29 | 2013 |
| Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW) JH Lau, CJ Zhan, PJ Tzeng, CK Lee, MJ Dai, HC Chien, YL Chao, W Li, ... International Symposium on Microelectronics 2011 (1), 000446-000454, 2011 | 27 | 2011 |
| Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP CJ Zhan, PJ Tzeng, JH Lau, MJ Dai, HC Chien, CK Lee, ST Wu, KS Kao, ... 2012 IEEE 62nd Electronic Components and Technology Conference, 548-554, 2012 | 25 | 2012 |
| Thermo-mechanical analysis of thermoelectric modules SL Li, CK Liu, CY Hsu, MC Hsieh, MJ Dai, ST Wu 2010 5th International Microsystems Packaging Assembly and Circuits …, 2010 | 25 | 2010 |
| Thermo-mechanical simulative study for 3D vertical stacked IC packages with spacer structures MC Hsieh, CK Yu, ST Wu 2010 26th Annual IEEE Semiconductor Thermal Measurement and Management …, 2010 | 25 | 2010 |
| Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV) HC Chien, JH Lau, YL Chao, RM Tain, MJ Dai, ST Wu, WC Lo, MJ Kao Journal of microelectronics and electronic packaging 9 (2), 97-103, 2012 | 24 | 2012 |
| Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips ST Wu, HC Chien, JH Lau, M Li, J Cline, M Ji 2013 IEEE 63rd Electronic Components and Technology Conference, 1471-1479, 2013 | 22 | 2013 |
| An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications YM Lin, ST Wu, WW Shen, SY Huang, TY Kuo, AY Lin, TC Chang, ... 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 349-354, 2018 | 20 | 2018 |
| Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration MC Hsieh, ST Wu, CJ Wu, JH Lau, RM Tain, WC Lo 2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and …, 2011 | 16 | 2011 |
| Low-cost TSH (through-silicon hole) interposers for 3D IC integration JH Lau, CK Lee, CJ Zhan, ST Wu, YL Chao, MJ Dai, RM Tain, HC Chien, ... 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 290-296, 2014 | 15 | 2014 |
| Evaluation of temperature-dependent effective material properties and performance of a thermoelectric module HC Chien, ET Chu, HL Hsieh, JY Huang, ST Wu, MJ Dai, CK Liu, DJ Yao Journal of electronic materials 42, 2362-2370, 2013 | 14 | 2013 |
| Equivalent mechanical properties of through silicon via interposers–A unit model approach C Chen, ST Wu Microelectronics Reliability 55 (1), 221-230, 2015 | 12 | 2015 |
| Design, fabrication, and calibration of stress sensors embedded in a TSV interposer in a 300mm wafer PJ Tzeng, JH Lau, MJ Dai, ST Wu, HC Chien, YL Chao, CC Chen, ... 2012 IEEE 62nd Electronic Components and Technology Conference, 1731-1737, 2012 | 12 | 2012 |
| Thinned integrated circuit device and manufacturing process for the same ST Wu, HC Chien, JH Lau, YL Chao, WC Lo US Patent 9,252,054, 2016 | 11 | 2016 |
| Multi-chip package and manufacture method thereof CJ Chen, YM Lin, ST Wu, S Huang, AY Lin, TH Ni, YY Lo US Patent 11,424,190, 2022 | 10 | 2022 |
| Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs ST Wu, JH Lau, HC Chien, JF Hung, MJ Dai, YL Chao, RM Tain, WC Lo, ... 2012 IEEE 62nd Electronic Components and Technology Conference, 1618-1624, 2012 | 9 | 2012 |
| Thermal performance of 3D IC integration with Through-Silicon Via (TSV) HC Chien, JH Lau, YL Chao, RM Tain, MJ Dai, ST Wu, WC Lo, MJ Kao International Symposium on Microelectronics 2011 (1), 000025-000032, 2011 | 9 | 2011 |
| An RDL-first fan-out panel-level package for heterogeneous integration applications YM Lin, ST Wu, CM Wang, CH Lee, SY Huang, AY Lin, TC Chang, PB Lin, ... 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 1463-1469, 2019 | 8 | 2019 |
Heng-Chieh ChienIndustrial Technology Research institute在 itri.org.tw 的电子邮件经过验证
