Rapidly growing demand for broadband-cellular-data traffic is driving fifth-generation (5G) wireless standardization towards the deployment of gigabit-per-second mm-Wave technology by 2020. Paving the road to 5G, 200m coverage in non-line-of-sight (NLOS) urban cells was demonstrated using practical antenna arrays at 28GHz [1], and the FCC recently issued a notice of inquiry into the provision of mobile services above 24GHz. Battery life and thermal limitations make power efficiency critical in the envisioned user-equipment (UE) phased-array transceivers, particularly for power amplifiers (PAs), which operate at 8-to-10dB power back-off (PBO) to transmit broadband, high-peak-to-average power-ratio (PAPR) signals with high fidelity. Higher yields and lower costs for integrated phased arrays make CMOS the preferred choice over other more-power-efficient technologies, e.g. GaAs. Furthermore, calibrating an integrated array of PAs, e.g. by using digital pre-distortion, is prohibitively complex for high-volume manufacturing. Thus, maximizing PAE of inherently linear CMOS PA circuits at PBO is a major challenge for future 5G UE radios.