A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking
IEEE Journal of Solid-State Circuits, 2011•ieeexplore.ieee.org
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with
50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation,
achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through
micro bumps and test pads have been developed. Block based dual period refresh scheme
is applied to reduce self refresh current with minimum chip size burden. Stacking of 2 dies
with 7.5 μm diameter and 40 μm pitch TSVs has been fabricated and tested, which results in …
50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation,
achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through
micro bumps and test pads have been developed. Block based dual period refresh scheme
is applied to reduce self refresh current with minimum chip size burden. Stacking of 2 dies
with 7.5 μm diameter and 40 μm pitch TSVs has been fabricated and tested, which results in …
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through micro bumps and test pads have been developed. Block based dual period refresh scheme is applied to reduce self refresh current with minimum chip size burden. Stacking of 2 dies with 7.5 μm diameter and 40 μm pitch TSVs has been fabricated and tested, which results in 76% overall package yield without difference in performances between top and bottom die.
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