This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. This frequency synthesizer is fully compliant with IEEE 802.15.3c normalization [1–4]. This PLL delivers a quadrature LO signal around 20GHz and a differential LO signal around 40GHz and has 17.9% tuning range. The wide tuning range of 17.9% permits to cover the full IEEE 802.15.3c band with industrial margin. The phase noise is −100dBc/Hz at 1MHz offset and the total power dissipation is only 80mW including the output buffers and amplifiers. Short-range wireless multi-Gb/sec communication systems use the mm-wave band of 57GHz to 66GHz, according to the IEEE 802.15.3c normalization. The frequency synthesis is one of the key elements for these transceivers. Indeed, one must take into account the antagonist tradeoff between large band tuning range of the frequency synthesizer and phase noise performance. In transceivers using super-heterodyne architecture with double conversion, the frequency synthesizer signal fLO can be equal to 2fRF /3 and fRF /3. In this case, to cover the four channels of the IEEE 802.15.3c normalization, the frequency synthesizer has to deliver a first local oscillator (LO) signal between 19.44GHz and 21.6GHz and a second LO signal between 38.88GHz and 43.2GHz, respectively. This architecture offers a good trade off between the required large frequency tuning range (≫15%) and low phase noise (≪−95dBc/Hz).