Digital Modulators is one of the areas that have received great attention recently due to the tremendous developments in Radio Frequency (RF) frond ends and system on chips (soc) architecture in general. Building any kind of digital modulators using soc type Field Programmable Gate Array (FPGA), like ZYBO, depends heavily on how the carrier signal got generated since it consumes a lot of utilization recourses. This paper presents a new method of generating sinusoidal carrier signal based on Direct Digital Synthesizer (DDS) concept using small size Look Up Table (LUT). 64 samples of a quarter period of the sine wave signal were stored in a fixed point format in small LUT to generate the carrier at the desire frequency. The paper used Very high speed integrated circuit Hardware Descriptive Language (VHDL) without the help of DSP Builder Tools or XILINX System Generator. The suggested method was tested by building simple modulators like On-Off Keying (OOK) and Amplitude Shift Keying (ASK). Low utilization was achieved as compared to other implementation methods.