Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate
In present work a new XNOR gate using three transistors has been presented, which shows
power dissipation of 550.7272$\mu $ W in 0.35$\mu $ m technology with supply voltage of
3.3 V. Minimum level for high output of 2.05 V and maximum level for low output of 0.084 V
have been obtained. A single bit full adder using eight transistors has been designed using
proposed XNOR cell, which shows power dissipation of 581.542$\mu $ W. Minimum level
for high output of 1.97 V and maximum level for low output of 0.24 V is obtained for sum …
power dissipation of 550.7272$\mu $ W in 0.35$\mu $ m technology with supply voltage of
3.3 V. Minimum level for high output of 2.05 V and maximum level for low output of 0.084 V
have been obtained. A single bit full adder using eight transistors has been designed using
proposed XNOR cell, which shows power dissipation of 581.542$\mu $ W. Minimum level
for high output of 1.97 V and maximum level for low output of 0.24 V is obtained for sum …
In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272W in 0.35m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542W. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35m CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit's shows better performance in terms of power consumption and transistor count.
arxiv.org
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