Supply current test is well established for digital CMOS circuits and the advantages of improved observability and reliability indication have prompted its use for analogue and mixed signal circuits. A short review of the literature on this subject is given. Fault simulation is used for the investigation of dynamic supply current test of a PLL, confirming existing results from smaller circuits that a combination of supply current and output voltage monitoring leads to higher fault coverage. In the paper, fault coverage is further improved, using crosscorrelation of the supply current and output signals, and the potential for BIST implementation of this technique is demonstrated using low resolution polarised crosscorrelation. Fault simulation is also performed on an analogue multiplier to investigate the effect of process parameter deviations on the supply current. The fault coverage is found to be improved by removing the DC component of the signal. Encouraging results are obtained from the application of supply current test techniques to a commercial mixed signal ASIC currently beyond the capabilities of analogue fault simulation, indicating that efforts at improving fault simulation in this area are worthwhile. The requirements for fault modelling and simulation to support supply current test are discussed and some initial results of accelerating this process using macromodelling are presented.