Jointly designed architecture-aware LDPC convolutional codes and memory-based shuffled decoder architecture

YL Ueng, YL Wang, LS Kan, CJ Yang… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
In this paper, we jointly design architecture-aware (AA) low-density parity-check
convolutional codes (LDPC-CCs) and the associated memory-based decoder architecture …

Jointly designed architecture-aware LDPC convolutional codes and high-throughput parallel encoders/decoders

Z Chen, TL Brandon, DG Elliott, S Bates… - … on Circuits and …, 2009 - ieeexplore.ieee.org
A novel design approach is proposed for low-density parity-check convolutional codes
(LDPC-CCs), that jointly optimizes the code, encoder and decoder to achieve high …

Efficient implementation of low-density parity-check convolutional code encoders with built-in termination

Z Chen, TL Brandon, S Bates, DG Elliott… - … on Circuits and …, 2008 - ieeexplore.ieee.org
Low-density parity-check convolutional codes (LDPC-CCs) have demonstrated comparable
error-correcting performance to LDPC block codes (LDPC-BCs). However, the LDPC-CC …

Capacity-approaching TQC-LDPC convolutional codes enabling power-efficient decoders

E Pisek, D Rajan, S Abu-Surra… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In this paper, we develop a new capacity-approaching code, namely, parallel-concatenated
(PC)-Low Density Parity Check (LDPC) convolutional code that is based on the parallel …

Low-power LDPC-CC decoding architecture based on the integration of memory banks

I Yoo, IC Park - IEEE Transactions on Circuits and Systems II …, 2016 - ieeexplore.ieee.org
This brief proposes a low-power low-density parity check convolutional code (LDPC-CC)
decoder that is fully compatible with the IEEE 1901 standard. The proposed architecture …

Implementation aspects of LDPC convolutional codes

AE Pusane, AJ Feltstrom, A Sridharan… - IEEE Transactions …, 2008 - ieeexplore.ieee.org
Potentially large storage requirements and long initial decoding delays are two practical
issues related to the decoding of low-density parity-check (LDPC) convolutional codes using …

Trellis-based QC-LDPC convolutional codes enabling low power decoders

E Pisek, D Rajan, JR Cleveland - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
In this paper, we propose a new type of code called Trellis-based Quasi-Cyclic (TQC)-LDPC
convolutional code, which is a special case of protograph-based LDPC convolutional codes …

High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule

S Kumawat, R Shrestha, N Daga… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This paper presents architecture of block-level-parallel layered decoder for irregular LDPC
code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11 …

A low-cost serial decoder architecture for low-density parity-check convolutional codes

S Bates, Z Chen, L Gunthorpe… - … on Circuits and …, 2008 - ieeexplore.ieee.org
We propose a low-cost serial decoder architecture for low-density parity-check convolutional
codes (LDPC-CCs). It has been shown that LDPC-CCs can achieve comparable …

High throughput parallel decoder design for LDPC convolutional codes

Z Chen, S Bates, W Krzymien - 2008 4th IEEE International …, 2008 - ieeexplore.ieee.org
LDPC convolutional code (LDPC-CC) decoders are composed of processors, making them
parallel in the iteration dimension. However, for time-varying LDPC-CCs, each individual …