… cannot be controlled. Along with downscaling, wet etching became less suitable for the
definition of small patterns and an increasing interest grew towards plasma etching processes. …

… high-resolution patterning to create sub-10 nm structures in the resist, (7) it is difficult to pattern
these with high density, for example, with sub-10 nm … a sub-10 nm gate length defined by …

… 1(d)], which shows that G2 is shifted toward contact C3. GS constitutes a new challenge for …
that the resist patterns shrinked laterally and vertically (of about 10 nm after 30 s plasma), and …

… pattern experiment consists of (Si 10 nm/Si 0.7 Ge 0.3 10 nm… -diameter SOI substrates (Si
15 nm–SiO 2 20 nm/Si bulk) in an … tend toward that of the HF deoxidized sample of 3.9 nm/min …

… The former present a high selectivity towards silicon oxide but have differences between …
, the pattern dimensions reach the sub-10 nm range. A very tight profile control is therefore …

… band to be shifted either towards or away from the Fermi … tri-gate transistors, self-aligned
contacts and high density MIM … A 10 nm high performance and low-power CMOS technology …

… treated with a H2 plasma [19]. Surface modification of deposition-… margin for dual metal
gate patterning. (b) Dual metal … tri-gate transistors, self-aligned contacts and high density MIM …

… is observed only when scaled beyond a cell size of 10 nm 2 (ref. ). … Our work is a step towards
implementing the 1T1R … deposited using sputtering and patterned using photolithography. …

… and pattern density continue to increase in sub-7 nm technology … toward the surface in order
to account for this artifact, then … , ∼10 nm of the spacer is etched from the top of the silicon …

… From this perspective, an ultimate fabrication route toward SiNC arrays provides control …
the hybrid patterned silicon substrates was performed in an inductively coupled plasma etcher (…