… logic circuits with NC-FinFETs, we evaluate the standby-power/switching-energy/delay
performance of a fivestage … The negative differential output conductance due to the inverse Vds-…

… mV for a differential input voltage of 5 mV. … circuits but it costs additional area and increases
delay [14,15,16]. A high-speed DTDC with the hybrid amplification stage and new latch stage …

… stage dynamic comparators directly stack the input transistors with the cross-coupled latch
circuit… The voltage difference between Dn and Dp builds up the initial differential voltage at the …

… The circuit is generally suffered from high power dissipation and low comparison speed. …
In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to …

… The realization of the basic logic gates in differential CML and … buffer for design of multi-stage
applications. Chapter 5 deals … subthreshold MOS current mode logic circuits using a novel …

… These circuitry ideas lead to an improvement in the amplifier’s specifications, such as dc …
first stage was configured based on a current mirror topology in which the proposed differential …

… Our introduction to circuit simulation in this chapter uses SPICE (simulation program with
integrated circuit emphasis). The introduction is used to review basic circuit analysis and to …

… 6(a), the maximum gate delay is 1.3 ms, leading down to Hz-range operation as in DLS logic
under deep microarchitectures with several tens of gates per pipeline stage. Also, the power…

… Some outputs of reversible gates are not used in next stage and also they are not stored.
Garbage … True differential operation can be obtained by an alternative logic design called MOS …

… from other memristor-based logic circuits (depending on the … are based on a variety of
differential TL circuits, such as [41] … of multi-stage CMOS logic, with an equivalent TLG circuit, can …