Retention-aware DRAM auto-refresh scheme for energy and performance efficiency

WK Cheng, PY Shen, XL Li - Micromachines, 2019 - mdpi.com
… Furthermore, to skip refresh non-weak rows, we accessed and increased the … refresh scheme
can properly improve the system performance and have a great reduction in DRAM refresh

Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation

H Choi, D Hong, J Lee, S Yoo - Microprocessors and Microsystems, 2020 - Elsevier
Refresh power of dynamic random-access memory (DRAM) … time, if we can increase the
refresh period of the DRAM chip by at … We perform parallel profiling while a DRAM chip is in idle …

Charge-aware DRAM refresh reduction with value transformation

S Kim, W Kwak, C Kim, D Baek… - … on High Performance …, 2020 - ieeexplore.ieee.org
… the performance penalty of refresh by scheduling optimization of memory commands and
parallelization of refresh with accesses. … This paper increase the scope of value-based refresh

Access-aware per-bank DRAM refresh for reduced DRAM refresh overhead

ÉF Zulian, C Weis, N Wehn - 2020 IEEE International …, 2020 - ieeexplore.ieee.org
… amplify the effects Access-Aware Per-bank DRAM Refresh: (1) The increase of RACThist
length. (… bank parallelism, hence accesses are more evenly distributed among banks as well as …

Nonblocking DRAM refresh

K Nguyen, K Lyu, X Meng, V Sridharan, X Jian - IEEE Micro, 2019 - ieeexplore.ieee.org
… read accesses to refreshing data in DRAM while preserving … DRAM simulator, we simulated
various NASA Parallel, Parsec, … that increasing DRAM density often requires reducing DRAM

DR refresh: Releasing DRAM potential by enabling read accesses under refresh

Y Cao, C Li, J Wang, W Zhang, Q Chen… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
… mechanism which operates the same row on all DRAM … under DR refresh mechanism can
parallelize refresh operation … read and write performance, we focus on improving memory read …

The colored refresh server for DRAM

X Pan, F Mueller - 2019 IEEE 22nd International Symposium on …, 2019 - ieeexplore.ieee.org
… Mutlu, “Improving dram performance by parallelizing refreshes with accesses,” in International
Symposium on High Performance Computer Architecture, Feb 2014, pp. 356–367. [34] …

Crow: A low-cost substrate for improving dram performance, energy efficiency, and reliability

H Hassan, M Patel, JS Kim, AG Yaglikci… - Proceedings of the 46th …, 2019 - dl.acm.org
DRAM access latency, reduce the refresh overhead, and improve DRAM reliability with no
changes to the DRAM … A single DRAM chip contains multiple banks that operate in parallel. To …

Refresh triggered computation: Improving the energy efficiency of convolutional neural network accelerators

SMAH Jafri, H Hassan, A Hemani, O Mutlu - ACM Transactions on …, 2020 - dl.acm.org
parallelize accesses and refreshes via scheduling and … improves DRAM energy consumption
of workloads from different domains. We conclude that RTC largely mitigates DRAM refresh

Increasing DDR4 SDRAM throughput in parallel workloads

YA Nedbailo, IA Petrov - 2020 Moscow workshop on electronic …, 2020 - ieeexplore.ieee.org
Increasing average access size While we have just noted that look-ahead in the memory
controller is not a universal solution to reduce page switching rate in parallel … memory refreshes. …