A scalable high‐speed hybrid 1bit full adder design using XOR‐XNOR module

M Hasan, S Islam, M Hossain… - International Journal of …, 2021 - Wiley Online Library
… In this work, a novel FA design, that combines the benefits of … For condition 1 of the 2-input
XNOR gate, p 7 and p 8 transistors … and XOR signals appear on the gates of p 3 and n 3 . …

A hybrid full adder design using multigate devices based on xor/xnor logic

VM Senthil Kumar, C Rathnakar, MA Guptha… - … System Design …, 2021 - Springer
… In this paper, the XOR/XNOR and XOR–XNOR circuits using CMOS and FinFET devices are
… A high speed 8 transistor full adder design using novel 3 transistor XOR gates. International …

A high-speed and scalable XOR-XNOR-based hybrid full adder design

M Hasan, MS Hussain, M Hossain, M Hasan… - Computers & Electrical …, 2021 - Elsevier
… p 3 and p 4 , XNOR output is pulled up to strong logic 1. … , n 4 transistor is ON (input A = 1)
and XNOR output is pulled … PMOS p 8 provides strong logic 1 to the gate of n 11 since IND = 1

Eight Bit Full Adder Design Using Fifteen Transistors With Novel Five Transistors XNOR Gate

P Sritha, P Geethamani - 2019 International Conference on …, 2019 - ieeexplore.ieee.org
adder, unit two is the XNOR module and unit three is the carry … 8-bit full adder has been
proposed by using 15 transistors with … The simulation results were carried out by using Cadence …

For Enhancing the Performance in Single Bit Hybrid Full Adder Circuits Using XNOR Gate

E Jadon, S Akashe - … International Conference, CNC 2020, Gwalior, India …, 2021 - Springer
single bit 16, 14, 10 and 8 transistor full adder designs are proposed in this paper. Key
purpose of the design is to swing fullThree most significant parameters of the VLSI system are …

High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell

J Kandpal, A Tomar, M Agarwal… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
… embedded in 2-, 4-, and 8-bit cascaded full adder (CFA) structures… the FA is designed in a
single module using MOS transistors. … A novel XOR–XNOR circuit is proposed in Section-II and …

Design and analysis of 8-bit ripple Carry Adder using nine Transistor Full Adder

GR Padmini, O Rajesh, K Raghu… - 2021 7th …, 2021 - ieeexplore.ieee.org
gates called Exclusive- OR gate and ExclusiveNOR gate. … -transistor model full adder is
designed using the above three … , "Single bit full adder design using 8 transistors with novel

An energy efficient 16t hybrid-cmos full adder using novel full swing xnor logic

KK Mishra, AK Dubey, V Varshney… - 2020 IEEE Students …, 2020 - ieeexplore.ieee.org
novel hybrid-CMOS 1-bit Full Adder based on XNOR-XNOR logic is presented. The XNOR
logic is proposed using 5 transistors. … III presents the proposed XNOR based novel design of …

[PDF][PDF] Energy Efficient Design of Full Adder using the XOR/XNOR Gates

K Gayathri, DS Poongodi - Grenze International Journal of …, 2022 - academia.edu
… Another 8-transistor XNOR gate with low power consumption … It is made up of three transistors:
one pMOS and two nMOS. … new design 6T Full Adder Circuit using Novel 2T XNOR Gates” …

A Novel 1-bit Fast and Low Power 17-T Full Adder Circuit

K Gupta, R Tiwari, N Singh, A Agrawal… - 2024 IEEE …, 2024 - ieeexplore.ieee.org
transistor size is used. This improved XOR-XNOR circuit is also used in the four different Full
Adder … schematic on cadence virtuoso software using 8 pmos and 9 nmos transistors and …