… high-resolution patterning to create sub-10 nm structures in the resist, (7) it is difficult to pattern
these with high density, for example, with sub-10 nm … a sub-10 nm gate length defined by …

… pattern experiment consists of (Si 10 nm/Si 0.7 Ge 0.3 10 nm… -diameter SOI substrates (Si
15 nm–SiO 2 20 nm/Si bulk) in an … tend toward that of the HF deoxidized sample of 3.9 nm/min …

… treated with a H2 plasma [19]. Surface modification of deposition-… margin for dual metal
gate patterning. (b) Dual metal … tri-gate transistors, self-aligned contacts and high density MIM …

… of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, … the
complexity of such patterning processes. For the latter, we review the use of both high-k and low…

… is observed only when scaled beyond a cell size of 10 nm 2 (ref. ). … Our work is a step towards
implementing the 1T1R … deposited using sputtering and patterned using photolithography. …

… From this perspective, an ultimate fabrication route toward SiNC arrays provides control …
the hybrid patterned silicon substrates was performed in an inductively coupled plasma etcher (…

… -10 nm features reported in these works are only defined on the resist. High-fidelity pattern
transfer is also significant to sub-10 nm … in pattern transfer to fulfill the fabrication of sub-10 nm …

… Tailoring of plasma chemistry yielded benefits to patterning … Looking toward the future,
quantum computing is a potential … plasma ion doping of Si and Sn into InGaAs in high density …

… widely used for patterning nanogaps at the sub-10 nm level due to … nm light from an intense
EUV source is directed toward a … a better choice for high density nanoscale patterning. [ 63 ] …

… For further scaling below the 10 nm node, if EUV is not used, … beyond plasma ALD of SiO 2
for self-aligned patterning. With … enhancing the flux of species toward the wafer, respectively. …