A 21-dBm 3.7 W/mm² 28.7% PAE 64-GHz power amplifier in 22-nm FD-SOI
This letter presents the design of a 64-GHz power amplifier (PA) in a 22-nm FD-SOI CMOS
technology. Benefiting from optimized pseudodifferential cascode gain cells as well as the …
technology. Benefiting from optimized pseudodifferential cascode gain cells as well as the …
Design of a Compact Power Amplifier with 18.6 dBm 60 GHz 20.5% PAE in 22 nm FD-SOI
This paper presents the design of a 60 GHz power amplifier (PA) in a 22 nm FD-SOI CMOS
technology. To improve the performance at millimeter-wave frequencies by minimizing the …
technology. To improve the performance at millimeter-wave frequencies by minimizing the …
A 62-GHz High-Efficiency Power Amplifier With Modulation Capability via Back-Gate in 22-nm FD-SOI
This letter presents a feasibility study for a 62-GHz power amplifier (PA) in a 22-nm CMOS
technology with integrated data modulation via the back-gate. The proposed PA consists of …
technology with integrated data modulation via the back-gate. The proposed PA consists of …
A 21-39.5 GHz power amplifier for 5G wireless systems in 22 nm FD-SOI CMOS
This paper presents a high-gain broadband power amplifier for 5G wireless systems, which
provides a gain above 10 dB from 21 GHz to 39.5 GHz, and is implemented in a 22 nm FD …
provides a gain above 10 dB from 21 GHz to 39.5 GHz, and is implemented in a 22 nm FD …
A 28GHz two-way current combining stacked-FET power amplifier in 22nm FD-SOI
We present a two-way current combining power amplifier (PA) for 28GHz wireless
communication. To boost the saturated output power (P SAT) and maintain a high power …
communication. To boost the saturated output power (P SAT) and maintain a high power …
A 28 GHz 22FDX® PA with 31.5% Peak PAE and Output Power of 21 dBm in CW, 18.5 dBm in QPSK, and 12.5 dBm in 64QAM
A 22nm FD-SOI Power Amplifier (PA) for 5G communication at 28 GHz is demonstrated. A
dual-stage approach together with stacking techniques and optimized transistor …
dual-stage approach together with stacking techniques and optimized transistor …
A 97–107 GHz Triple-Stacked-FET Power Amplifier with 23.7dB Peak Gain, 15.1dBm PSAT, and 18.6% PAEMAX in 28-nm FD-SOI CMOS
A 97–107 GHz power amplifier (PA) based on a stacked-FET topology is presented. In a
triple-stacked-FeT structure, stacking efficiency is analyzed using four combinations of series …
triple-stacked-FeT structure, stacking efficiency is analyzed using four combinations of series …
A 1.2 V 20 dBm 60 GHz power amplifier with 32.4 dB gain and 20% peak PAE in 65nm CMOS
A Larie, E Kerhervé, B Martineau… - ESSCIRC 2014-40th …, 2014 - ieeexplore.ieee.org
A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP)
CMOS technology. The structure consists of four common-source pseudo-differential stages …
CMOS technology. The structure consists of four common-source pseudo-differential stages …
A 22nm FD-SOI CMOS 2-way D-band Power Amplifier Achieving PAE of 7.7% at 9.6 dBm OP1dB and 3.1% at 6dB Back-off by Leveraging Adaptive Back-Gate Bias …
This work presents a 2-way 3-stage D-band Power Amplifier (PA) in 22nm FD-SOI
technology. A dynamic 3-stage bias scaling technique is proposed for this PA. It is based on …
technology. A dynamic 3-stage bias scaling technique is proposed for this PA. It is based on …
A 19.1% PAE, 22.4-dBm 53-GHz parallel power combining power amplifier with stacked-FET techniques in 90-nm CMOS
WC Sun, CN Kuo - 2019 IEEE MTT-S International Microwave …, 2019 - ieeexplore.ieee.org
A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-
nm bulk CMOS. The output stage is optimized to achieve high output power while …
nm bulk CMOS. The output stage is optimized to achieve high output power while …