High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell
Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid
FA in terms of delay, power, and driving capability is largely dependent on the performance …
FA in terms of delay, power, and driving capability is largely dependent on the performance …
Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder
M Amini-Valashani, M Ayat, S Mirzakuchaki - Microelectronics journal, 2018 - Elsevier
A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is
presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by …
presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by …
[HTML][HTML] Low voltage high performance hybrid full adder
P Kumar, RK Sharma - … Science and Technology, an International Journal, 2016 - Elsevier
This paper presents a low voltage and high performance 1-bit full adder designed with an
efficient internal logic structure that leads to have a reduced Power Delay Product (PDP) …
efficient internal logic structure that leads to have a reduced Power Delay Product (PDP) …
Low-power and fast full adder by exploring new XOR and XNOR gates
H Naseri, S Timarchi - IEEE transactions on very large scale …, 2018 - ieeexplore.ieee.org
In this paper, novel circuits for XOR/XNOR and simultaneous XOR-XNOR functions are
proposed. The proposed circuits are highly optimized in terms of the power consumption …
proposed. The proposed circuits are highly optimized in terms of the power consumption …
Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit
P Bhattacharyya, B Kundu, S Ghosh… - … Transactions on very …, 2014 - ieeexplore.ieee.org
In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–
semiconductor (CMOS) logic and transmission gate logic is reported. The design was first …
semiconductor (CMOS) logic and transmission gate logic is reported. The design was first …
A high-speed and scalable XOR-XNOR-based hybrid full adder design
This work presents the design of a scalable and full-swing Full Adder (FA) based on the
XOR-XNOR module. The performance of the design has been compared with eleven …
XOR-XNOR module. The performance of the design has been compared with eleven …
[HTML][HTML] Gate diffusion input technique based full swing and scalable 1-bit hybrid full adder for high performance applications
A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI)
technique and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic …
technique and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic …
Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design
S Wairya, RK Nagaria, S Tiwari - VLSI Design, 2012 - Wiley Online Library
This paper presents a comparative study of high‐speed and low‐voltage full adder circuits.
Our approach is based on hybrid design full adder circuits combined in a single unit. A high …
Our approach is based on hybrid design full adder circuits combined in a single unit. A high …
Low‐power high‐speed full adder for portable electronic applications
CK Tung, SH Shieh, CH Cheng - Electronics Letters, 2013 - Wiley Online Library
A low‐power, high‐speed full adder (FA), abbreviated as LPHS‐FA, is presented as an
elegant way to reduce circuit complexity and improve the performance thereof. Employing as …
elegant way to reduce circuit complexity and improve the performance thereof. Employing as …
Design of a scalable low-power 1-bit hybrid full adder for fast computation
A novel design of a hybrid Full Adder (FA) using Pass Transistors (PTs), Transmission Gates
(TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is …
(TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is …