Compact implementation of a 1-bit adder by coherent 2-beam excitation of a single plasmonic cavity

F Dell'Ova, Y Brûlé, N Gros, J Bizouard… - ACS …, 2024 - ACS Publications
We demonstrate experimentally the dual beam optical drive of an interconnect-free 2-input,
2-output 1-bit adder implemented inside a single gold plasmonic cavity, focused ion milled …

Interconnect-Free Multibit Arithmetic and Logic Unit in a Single Reconfigurable 3 μm2 Plasmonic Cavity

U Kumar, A Cuche, C Girard, S Viarbitskaya… - ACS …, 2021 - ACS Publications
Processing information with conventional integrated circuits remains beset by the
interconnect bottleneck: circuits made of smaller active devices need longer and narrower …

[HTML][HTML] Broadband plasmonic half-subtractor and digital demultiplexer in pure parallel connections

PY Wu, YC Chang, CB Huang - Nanophotonics, 2022 - degruyter.com
Nanophotonic arithmetic circuits requiring cascaded Boolean operations are difficult to
implement due to loss and footprint issues. In this work, we experimentally demonstrate …

[HTML][HTML] Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

C Lu, X Hu, H Yang, Q Gong - Scientific reports, 2014 - nature.com
Optical computing opens up the possibility for the realization of ultrahigh-speed and
ultrawide-band information processing. Integrated all-optical logic comparator is one of the …

Electrically driven highly tunable cavity plasmons

X He, J Tang, H Hu, J Shi, Z Guan, S Zhang… - ACS Photonics, 2019 - ACS Publications
Electrically driven ultrafast plasmon sources with narrow line width and wide-range
wavelength tunability are desirable choices for integrated nanophotonic circuits. These have …

Residue number system arithmetic based on integrated nanophotonics

J Peng, S Sun, VK Narayana, VJ Sorger… - Optics letters, 2018 - opg.optica.org
The residue number system (RNS) enables dimensionality reduction of an arithmetic
problem by representing a large number as a set of smaller integers, where the number is …

Feasibility of cascadable plasmonic full adder

M Fukuda, R Watanabe, Y Tonooka… - IEEE Photonics …, 2019 - ieeexplore.ieee.org
The concept and configuration of a plasmonic cascadable full adder are proposed, whose
logic operation is carried out by interference of surface plasmons and whose circuits are …

[HTML][HTML] Ultra-compact universal linear-optical logic gate based on single rectangle plasmonic slot nanoantenna

H Liu, Z Quan, Y Cheng, S Deng, L Yuan - Plasmonics, 2021 - Springer
Optical logic gates are key elements in all-optical circuits and computing. However, the
footprints of current optical logic gates are still on micrometer scale. There remains …

Multifunctional and multichannel all-optical logic gates based on the in-plane coherent control of localized surface plasmons

Z Zhu, J Yuan, L Jiang - Optics letters, 2020 - opg.optica.org
In this Letter, we report a scheme to design multifunctional and multichannel all-optical logic
gates based on the in-plane coherent control of localized surface plasmons in an Au …

[HTML][HTML] Cascaded logic gates in nanophotonic plasmon networks

H Wei, Z Wang, X Tian, M Käll, H Xu - Nature communications, 2011 - nature.com
Optical computing has been pursued for decades as a potential strategy for advancing
beyond the fundamental performance limitations of semiconductor-based electronic devices …