[PDF][PDF] Retiming of Synchronous Circuits with Variable Topology

A Nossek - academia.edu
circuit in order to apply combinational optimization to the … between retiming and the modification
of the circuit graph into … in order to find the most efficient circuit. Thus, the optimum AT1 …

Timed Petri nets with reset for pipelined synchronous circuit design

R Parrot, M Briday, OH Roux - … Conference on Applications and Theory of …, 2021 - Springer
This paper introduces an extension of Timed Petri Nets for the modeling of synchronous
electronic circuits, addressing pipeline design problems. Petri Nets have been widely used for …

Retiming for high-performance superconductive circuits with register energy minimization

TR Lin, M Pedram - Proceedings of the 39th International Conference on …, 2020 - dl.acm.org
… We perform the path-balancing retiming for a combinational circuit modeled by 𝐺(𝑉,𝐸) for
solving the CREM problem with performance constraints which is formulated as follows. …

Design and verification of pipelined circuits with Timed Petri Nets

R Parrot, M Briday, OH Roux - Discrete Event Dynamic Systems, 2023 - Springer
… on retiming, ie moving registers in the circuit without altering its behavior. Thanks to retiming
… Thanks to this accurate model of pipelined synchronous circuits, we present in Section 4 a …

General approach to asynchronous circuits simulation using synchronous fpgas

R Dashkin, R Manohar - … -Aided Design of Integrated Circuits …, 2021 - ieeexplore.ieee.org
circuits mapping onto the synchronous FPGAs. We build a synchronous model of the original
asynchronous circuit based … The proposed approach supports a wide range of circuit styles, …

Syncopation: an adaptive clock management technique for high-level synthesis generated circuits on FPGA

K Gibson - 2020 - open.library.ubc.ca
… operating frequency of synchronous circuits is determined … lead to circuits with reduced
performance compared to circuits … off retiming to implement Syncopation circuits. The baseline …

Improving Clock Frequencies in ASIC Designs through Semi-Automatic Register Placement and Advanced Retiming

M Hawich, SC Klein, T Stuckenberg… - … on Electronics & …, 2024 - ieeexplore.ieee.org
… Current application specific integrated circuit (ASIC) synthesis tools can to reposition these …
as ”retiming”. Historically, there have been two primary methods of approaching retiming. The …

VirtualSync+: Timing Optimization With Virtual Synchronization

GL Zhang, B Li, X Huang, X Yin, C Zhuo… - … of Integrated Circuits …, 2022 - ieeexplore.ieee.org
… improve circuit performance in the traditional paradigm is retiming, … the correct functional
behavior of circuits. The existing … the circuit under optimization is moved leftward with retiming to …

Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark

L Lagostina, F Minnella, J Cortadella… - … of Integrated Circuits …, 2024 - ieeexplore.ieee.org
… sequential elements in synchronous circuits, but their timing … -art retiming by exploiting four
types of synchronous sequential … Mix & Latch flow and a retiming performed with a state-of-the-…

Iterative and Verifiable Retiming for FPGA Performance Optimization

K Zhu, H Zhou, WS Luk, J Tao… - … Symposium of Electronics …, 2023 - ieeexplore.ieee.org
circuit performance since it determines the maximum operating frequency. Retiming is a
synchronous circuit … by moving registers across combinational circuit elements. Compared with …