… treated with a H2 plasma [19]. Surface modification of deposition-… margin for dual metal
gate patterning. (b) Dual metal … tri-gate transistors, self-aligned contacts and high density MIM …

… is observed only when scaled beyond a cell size of 10 nm 2 (ref. ). … Our work is a step towards
implementing the 1T1R … deposited using sputtering and patterned using photolithography. …

… From this perspective, an ultimate fabrication route toward SiNC arrays provides control …
the hybrid patterned silicon substrates was performed in an inductively coupled plasma etcher (…

… a significant transition toward planar vertically stacked gate-all-… We utilize a two-step oxidation
process, first patterning the first … Cr gate layer, vias are defined by lithography and plasma-…

… -10 nm features reported in these works are only defined on the resist. High-fidelity pattern
transfer is also significant to sub-10 nm … in pattern transfer to fulfill the fabrication of sub-10 nm …

… Tailoring of plasma chemistry yielded benefits to patterning … Looking toward the future,
quantum computing is a potential … plasma ion doping of Si and Sn into InGaAs in high density …

… widely used for patterning nanogaps at the sub-10 nm level due to … nm light from an intense
EUV source is directed toward a … a better choice for high density nanoscale patterning. [ 63 ] …

… ) applications, a high density of nanoscale transistors must to be … with Si 3 N 4 sidewall toward
gate-all-around application. The … , one to generate and control the plasma density by direct …

… it brought us towards the 3D fin shaped devices and the gate-all… Joubert, “Patterning of silicon
nitride for CMOS gate spacer … the silicon consumption in CH3F/O2/He high density plasmas…

… , we demonstrate smooth charge density patterns via spatially … We note that the spectrum is
shifted towards higher BE due … Following Ohmic contact formation, 10 nm Ti and 100 nm Au …