A survey on convolutional neural network accelerators: GPU, FPGA and ASIC

Y Hu, Y Liu, Z Liu - 2022 14th International Conference on …, 2022 - ieeexplore.ieee.org
convolutional neural network accelerators, and proposes future research trends. We summarize
the mainstream CNN accelerators, … In the future, accelerators for training will become the …

A survey of FPGA-based accelerators for convolutional neural networks

S Mittal - Neural computing and applications, 2020 - Springer
… Deep convolutional neural networks (CNNs) have recently shown very high accuracy in a
… Given the high computational demands of CNNs, custom hardware accelerators are vital for …

A survey of accelerator architectures for 3D convolution neural networks

S Mittal - Journal of Systems Architecture, 2021 - Elsevier
… , executing them on accelerators designed for 2D CNNs … In this paper, we present a
survey of hardware acceleratorsconvolution and not those that perform only 2D convolution

Designing novel AAD pooling in hardware for a convolutional neural network accelerator

K Khalil, O Eldash, A Kumar… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
… reconfigurable accelerator for deep convolutional neural net… on eight-layer convolutional
neural network with leaky rectified … based on the convolution neural network with rank based …

WinoNN: Optimizing FPGA-based convolutional neural network accelerators using sparse Winograd algorithm

X Wang, C Wang, J Cao, L Gong… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
… In this article, we propose a novel accelerator called WINONN. We fully discuss the chal…
Our high scalability design enables us to deploy sparse Winograd accelerators on very small …

GoSPA: An energy-efficient high-performance globally optimized sparse convolutional neural network accelerator

C Deng, Y Sui, S Liao, X Qian… - 2021 ACM/IEEE 48th …, 2021 - ieeexplore.ieee.org
… in convolutional neural network (CNN) models makes sparsity-aware CNN hardware designs
very attractive. The existing sparse CNN accelerators … sparse 2-D convolution, this paper …

An evaluation of edge tpu accelerators for convolutional neural networks

A Yazdanbakhsh, K Seshadri, B Akin… - arXiv preprint arXiv …, 2021 - research.google
… Edge TPUs are a domain of accelerators for low-power,edge … across 423K uniqueconvolutional
neural networks. Building upon … metrics ofEdge TPU accelerators. These learned models …

Improving memory utilization in convolutional neural network accelerators

P Jokic, S Emery, L Benini - IEEE Embedded Systems Letters, 2020 - ieeexplore.ieee.org
… of convolutional neural networks (CNNs) has achieved vast improvements by introducing
larger and deeper network … -limited accelerator designs, which are often restricted to store all …

An FPGA-based energy-efficient reconfigurable convolutional neural network accelerator for object recognition applications

J Li, KF Un, WH Yu, PI Mak… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
convolutional neural network (CNN). In this Brief, we report an FPGA-based computation-efficient
reconfigurable CNN accelerator. It … that the proposed CNN accelerator achieves a peak …

An efficient and flexible accelerator design for sparse convolutional neural networks

X Xie, J Lin, Z Wang, J Wei - … on Circuits and Systems I: Regular …, 2021 - ieeexplore.ieee.org
… Plenty of existing accelerators are built for dense CNNs or … sparse accelerators on FPGAs,
the proposed accelerator can … Compared to prior dense accelerators, this accelerator can …