RF performance and intertier coupling of CMOS processed in 3-D sequential integration are
investigated. pMOS transistor fabricated with a 500° C thermal budget features good RF …

RF performance of a fully integrated CMOS 3D Sequential Integration (3DSI) is, for the first
time, deeply investigated. We highlight that Top Tier PMOS processed at 630° C can feature …

For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub
22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si …

For the first time, CMOS TFTs of 65 nm channel length have been demonstrated by using a
novel microwave dopant activation technique. A low temperature microwave anneal is …

The race on the Complementary Metal-Oxide-Semiconductor (CMOS) More Moore
integration scale has brought to light several major limitations for efficient planar process …

For the first time, an in-depth analysis of the inter-tier dynamic coupling and RF crosstalk of
digital circuits in 3D sequential integration enables to conclude on the need of a Ground …

We report low V t (V t, Lg= 1μm=±0.26 V) high performance CMOS devices with ultra-scaled
T inv down to T inv~ 8Å using a gate-first dual Si/SiGe channel low-complexity integration …

This article explores the feasibility of high-temperature annealing for top-tier devices in a
sequential 3-D (Seq3D) technology. Thermally stable bottom-tier device and interconnect …

3D sequential integration requires top MOSFETs processed at low thermal budget, which
can impair the device reliability. In this work, top junction-less device are fabricated with a …

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which
can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated …