Testable realizations for FET stuck-open faults in CMOS combinational logic circuits

IEEE transactions on Computers, 1986 - ieeexplore.ieee.org
In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting
circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of …
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Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

SM Reddy, MK Reddy - IEEE Transactions on Computers, 1986 - computer.org
In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting
circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of …

Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

SM Reddy, MK Reddy - IEEE Transactions on Computers, 1986 - infona.pl
In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting
circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of …

Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

SM Reddy, MK Reddy - IEEE Transactions on Computers, 1986 - dl.acm.org
In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting
circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of …

[引用][C] Testable realizations for FET stuck-open faults in CMOS combinational logic circuits

SM REDDY, MK REDDY - IEEE transactions on computers, 1986 - pascal-francis.inist.fr
Testable realizations for FET stuck-open faults in CMOS combinational logic circuits CNRS Inist
Pascal-Francis CNRS Pascal and Francis Bibliographic Databases Simple search Advanced …

Testable realizations for FET stuck-open faults in CMOS combinational logic circuits

SM Reddy, MK Reddy - IEEE transactions on computers, 1986 - iro.uiowa.edu
In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting
circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of …

[引用][C] Testable realizations for FET stuck-open faults in CMOS combinational logic circuits

SM REDDY, MK REDDY - IEEE …, 1986 - Institute of Electrical and Electronics …