A bypassable scan flip-flop for low power testing with data retention capability

X Cao, H Jiao, EJ Marinissen - IEEE Transactions on Circuits …, 2021 - ieeexplore.ieee.org
The power consumption of modern highly complex chips during scan test is significantly
higher than the power consumed during functional mode. This leads to substantial heat …
被引用次数：8 相关文章

A Bypassable Scan Flip-Flop for Low Power Testing with Data Retention Capability

X Cao, H Jiao, EJ Marinissen - … on Circuits and Systems II: Express …, 2022 - research.tue.nl
The power consumption of modern highly complex chips during scan test is significantly
higher than the power consumed during functional mode. This leads to substantial heat …
[PDF] imec-publications.be

[PDF][PDF] A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

X Cao, H Jiao, EJ Marinissen - 2022 - imec-publications.be
The power consumption of modern highly complex chips during scan test is significantly
higher than the power consumed during functional mode. This leads to substantial heat …
[PDF] tue.nl

[PDF][PDF] A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

X Cao, H Jiao, EJ Marinissen - IEEE TRANSACTIONS ON CIRCUITS …, 2022 - pure.tue.nl
The power consumption of modern highly complex chips during scan test is significantly
higher than the power consumed during functional mode. This leads to substantial heat …
[PDF] tue.nl

[PDF][PDF] A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

X Cao, H Jiao, EJ Marinissen - IEEE TRANSACTIONS ON CIRCUITS …, 2022 - pure.tue.nl
The power consumption of modern highly complex chips during scan test is significantly
higher than the power consumed during functional mode. This leads to substantial heat …