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[PDF][PDF] Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop

R Jayagowri - International Journal of Computer Applications, 2015 - Citeseer
Power consumption of any circuit is high during test mode than its normal mode of
functioning. Different techniques are proposed to reduce the test power. This paper presents …
被引用次数：2 相关文章

[引用][C] Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop

R Jayagowri - International Journal of Computer …, 2015 - ui.adsabs.harvard.edu
Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop -
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