A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor

DH Kwon, YS Park, WY Choi - IEEE Transactions on Circuits …, 2015 - ieeexplore.ieee.org
We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level
bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be …
被引用次数：13 相关文章

A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor

DH Kwon, YS Park, WY Choi - IEEE Transactions on …, 2015 - yonsei.elsevierpure.com
We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level
bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be …

A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor

DH Kwon, YS Park, WY Choi - IEEE Transactions on Circuits and Systems I …, 2015 - infona.pl
We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level
bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be …
[PDF] yonsei.ac.kr

[PDF][PDF] A Clock and Data Recovery Circuit With Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor

DH Kwon, YS Park, WY Choi - IEEE TRANSACTIONS ON …, 2015 - tera.yonsei.ac.kr
We demonstrate a clock and data recovery (CDR) cir-cuit having a new type of a multi-level
bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be …