Single transistor eeprom memory cell
N Challa - US Patent 5,222,040, 1993 - Google Patents
A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control
gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area …
gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area …
Single transistor EEPROM memory cell
N Challa - US Patent 5,222,040, 1993 - freepatentsonline.com
A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control
gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area …
gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area …