A robust, fast pulsed flip-flop design

A Venkatraman, R Garg, SP Khatri - Proceedings of the 18th ACM Great …, 2008 - dl.acm.org
High Speed VLSI design utilizes heavy pipelining, resulting in a large number of flip-flops in
the circuit. Hence there is a strong motivation to design fast, low power and area efficient flip …
被引用次数：21 相关文章
[PDF] tamu.edu

[PDF][PDF] A Robust, Fast Pulsed Flip-Flop Design

A Venkatraman, R Garg, SP Khatri - 2008 - people.engr.tamu.edu
High Speed VLSI design utilizes heavy pipelining, resulting in a large number of flip-flops in
the circuit. Hence there is a strong motivation to design fast, low power and area efficient flip …
[PDF] archive.org

[PDF][PDF] A Robust, Fast Pulsed Flip-Flop Design

A Venkatraman, R Garg, SP Khatri - 2008 - scholar.archive.org
High Speed VLSI design utilizes heavy pipelining, resulting in a large number of flip-flops in
the circuit. Hence there is a strong motivation to design fast, low power and area efficient flip …
[PDF] psu.edu

[PDF][PDF] A Robust, Fast Pulsed Flip-Flop Design

A Venkatraman, R Garg, SP Khatri - 2008 - Citeseer
High Speed VLSI design utilizes heavy pipelining, resulting in a large number of flip-flops in
the circuit. Hence there is a strong motivation to design fast, low power and area efficient flip …