VLSI architecture for low latency radix-4 CORDIC
AS Dhar - Computers & Electrical Engineering, 2011 - Elsevier
The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has
been refined in terms of throughput and latency with the introduction of redundant arithmetic …
been refined in terms of throughput and latency with the introduction of redundant arithmetic …
VLSI architecture for low latency radix-4 CORDIC
B Lakshmi, AS Dhar - Computers and Electrical Engineering, 2011 - dl.acm.org
The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has
been refined in terms of throughput and latency with the introduction of redundant arithmetic …
been refined in terms of throughput and latency with the introduction of redundant arithmetic …
VLSI architecture for low latency radix-4 CORDIC
B Lakshmi, AS Dhar - Computers and Electrical Engineering, 2011 - infona.pl
The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has
been refined in terms of throughput and latency with the introduction of redundant arithmetic …
been refined in terms of throughput and latency with the introduction of redundant arithmetic …