A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18- CMOS

LJ Chen, SI Liu - IEEE Transactions on Very Large Scale …, 2015 - ieeexplore.ieee.org
Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-μm CMOS
process are presented. The proposed TADC uses a voltage-to-time converter (VTC) with a …
被引用次数：22 相关文章

A 12-bit 3.4 MS/s two-step cyclic time-domain ADC in 0.18-μm CMOS

LJ Chen, SI Liu - IEEE Transactions on Very Large Scale Integration …, 2016 - computer.org
Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-μm CMOS
process are presented. The proposed TADC uses a voltage-to-time converter (VTC) with a …

A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18- CMOS

LJ Chen, SI Liu - IEEE Transactions on Very Large Scale Integration …, 2016 - dl.acm.org
Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-CMOS
process are presented. The proposed TADC uses a voltage-to-time converter (VTC) with a …