RF characterization and modelling of high density through silicon vias for 3D chip stacking

L Cadix, C Bermond, C Fuchs, A Farcy, P Leduc… - Microelectronic …, 2010 - Elsevier
3D integration including Through Silicon Vias is more and more considered as the solution
to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are …

[引用][C] RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

L Cadix, C Bermond, C Fuchs, A Farcy… - Microelectronic …, 2010 - cir.nii.ac.jp

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

L Cadix, C Bermond, C Fuchs, A Farcy… - Microelectronic …, 2010 - dl.acm.org
3D integration including Through Silicon Vias is more and more considered as the solution
to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are …

[引用][C] RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking

L Cadix, A Farcy, C Bermond, C Fuchs… - Microelectronic …, 2010 - hal.univ-smb.fr
"RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking" -
Université Savoie Mont Blanc Accéder directement au contenu Documentation FR Français …

[引用][C] RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking

L Cadix, A Farcy, C Bermond, C Fuchs… - Microelectronic …, 2010 - inria.hal.science
"RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking"
- Inria - Institut national de recherche en sciences et technologies du numérique Accéder …

[引用][C] RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking

L Cadix, A Farcy, C Bermond… - Microelectronic …, 2010 - hal.univ-grenoble-alpes.fr
"RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking" -
Université Grenoble Alpes Accéder directement au contenu Documentation FR Se connecter …

RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking

L Cadix, A Farcy, C Bermond, C Fuchs… - Microelectronic …, 2010 - hal.science
3D integration including Through Silicon Vias is more and more considered as the solution
to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are …

[引用][C] RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

L CADIX, C BERMOND, B FLECHET… - Microelectronic …, 2010 - pascal-francis.inist.fr
RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking
CNRS Inist Pascal-Francis CNRS Pascal and Francis Bibliographic Databases Simple …

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

L Cadix, C Bermond, C Fuchs, A Farcy, P Leduc… - Microelectronic …, 2010 - infona.pl
3D integration including Through Silicon Vias is more and more considered as the solution
to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are …

[引用][C] RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking

L Cadix, A Farcy, C Bermond, C Fuchs… - 18th Materials for …, 2009 - hal.univ-smb.fr
RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking -
Université Savoie Mont Blanc Accéder directement au contenu Documentation FR Français …