Fast acquisition clock and data recovery circuit with low jitter

R Zhang - IEEE journal of solid-state circuits, 2006 - ieeexplore.ieee.org
This paper presents a half-rate clock and data recovery circuit (CDR) that combines the fast
acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase …
被引用次数：22 相关文章

[引用][C] Fast Acquisition Clock and Data Recovery Circuit With Low Jitter

R Zhang, GS La Rue - IEEE Journal of Solid-State Circuits, 2006 - ui.adsabs.harvard.edu
Fast Acquisition Clock and Data Recovery Circuit With Low Jitter - NASA/ADS Now on home
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[引用][C] Fast Acquisition Clock and Data Recovery Circuit With Low Jitter

R Zhang, GS La Rue - IEEE Journal of Solid-State Circuits, 2006 - cir.nii.ac.jp
Fast Acquisition Clock and Data Recovery Circuit With Low Jitter | CiNii Research CiNii 国立
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[引用][C] Fast acquisition clock and data recovery circuit with low jitter

R ZHANG, GS LA RUE - IEEE journal of solid-state circuits, 2006 - pascal-francis.inist.fr
Fast acquisition clock and data recovery circuit with low jitter CNRS Inist Pascal-Francis CNRS
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[引用][C] Fast acquisition clock and data recovery circuit with low jitter

R ZHANG, GS LA RUE - … journal of solid …, 2006 - Institute of Electrical and Electronics …