A scalable network-on-chip microprocessor with 2.5 D integrated memory and accelerator

SM PD, J Lin, S Zhu, Y Yin, X Liu… - … on Circuits and …, 2017 - ieeexplore.ieee.org
This paper presents a 2.5 D integrated microprocessor die, memory die, and accelerator die
with 2.5 D silicon interposer I/Os. The use of such 2.5 D silicon interposer I/Os provide a …
被引用次数：42 相关文章

[引用][C] A Scalable Network-on-Chip Microprocessor With 2.5 D Integrated Memory and Accelerator

SM Pudukotai Dinakarrao, L Jie, S Zhu… - … on Circuits and …, 2017 - repositum.tuwien.at
reposiTUm: A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and
Accelerator reposiTUm ABOUT REPOSITUM HELP Login News Browse by Publication Types …
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[PDF][PDF] A Scalable Network-on-Chip Microprocessor With 2.5 D Integrated Memory and Accelerator

PD Sai Manoj, J Lin, S Zhu, Y Yin, X Liu… - … ON CIRCUITS AND …, 2017 - mason.gmu.edu
This paper presents a 2.5 D integrated microproces-sor die, memory die, and accelerator die
with 2.5 D silicon interposer I/Os. The use of such 2.5 D silicon interposer I/Os provide a …