A 0.23- Bias Instability and 1- Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL

J Zhao, X Wang, Y Zhao, GM Xia… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
This paper presents a silicon oscillating accelerometer (SOA) with a new CMOS readout
circuit architecture. A phase lock loop (PLL) with a hybrid and antinoise folding PFD is …
被引用次数：70 相关文章

[引用][C] A 0.23- Bias Instability and 1- Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL

J Zhao, X Wang, Y Zhao, GM Xia, AP Qiu… - IEEE Journal of Solid …, 2017 - cir.nii.ac.jp
A 0.23- $\mu \text{g}$ Bias Instability and 1- $\mu \text{g}/\surd $ Hz Acceleration Noise Density
Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL | CiNii …

[引用][C] A 0.23-mu text {g} Bias Instability and 1-mu text {g}/surd Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital …

J Zhao, X Wang, Y Zhao, GM Xia… - IEEE Journal of …, 2017 - ui.adsabs.harvard.edu
A 0.23- mu text{g} Bias Instability and 1- mu text{g}/surd Hz Acceleration Noise Density Silicon
Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL - NASA/ADS …