Modeling of elevated temperatures impact on single event transient in advanced CMOS logics beyond the 65-nm technological node
This work presents the modeling of the impact of elevated temperatures on the SET
occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The …
occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The …
Modeling of Elevated Temperatures Impact on Single Event Transient in Advanced CMOS Logics Beyond the 65-nm Technological Node
L Artola, G Hubert - IEEE Transactions on Nuclear Science, 2014 - infona.pl
This work presents the modeling of the impact of elevated temperatures on the SET
occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The …
occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The …
Modeling of Elevated Temperatures Impact on Single Event Transient in Advanced CMOS Logics Beyond the 65-nm Technological Node
L Artola, G Hubert - IEEE Transactions on Nuclear Science, 2014 - ui.adsabs.harvard.edu
This work presents the modeling of the impact of elevated temperatures on the SET
occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The …
occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The …
[PDF][PDF] Modeling of Elevated Temperatures Impact on Single Event Transient in Advanced CMOS Logics Beyond the 65-nm Technological Node
L Artola, G Hubert - academia.edu
This work presents the modeling of the impact of elevated temperatures on the SET
occurrence and characteristics in an IBM 65-nm Bulk CMOS technology. The calculations …
occurrence and characteristics in an IBM 65-nm Bulk CMOS technology. The calculations …