CMOS phase-locked loop circuits and hot carrier effects

Y Liu, A Srivastava - Journal of Low Power Electronics, 2012 - ingentaconnect.com
Three CMOS phase-locked loop (PLL) integrated circuits are designed in 0.5 μmn-well
CMOS process using single-ended voltage-controlled oscillator, differential voltage …
被引用次数：1 相关文章

[引用][C] CMOS Phase-Locked Loop Circuits and Hot Carrier Effects

Y LIU, A SRIVASTAVA - Journal of low power electronics …, 2012 - pascal-francis.inist.fr
CMOS Phase-Locked Loop Circuits and Hot Carrier Effects CNRS Inist Pascal-Francis CNRS
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[引用][C] CMOS Phase-Locked Loop Circuits and Hot Carrier Effects

Y LIU, A SRIVASTAVA - Journal of low power …, 2012 - American Scientific Publishers