3-D multilayer copper interconnects for high-performance monolithic devices and passives

A Ghannam, D Bourrier, L Ourak… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
IEEE Transactions on Components, Packaging and Manufacturing …, 2013ieeexplore.ieee.org
This paper presents a new and efficient low-cost multilayer 3-D copper interconnect process
for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated
with an optimized electroplating process to form multilevel 3-D interconnects in a single
metallization step. The SU-8 is used as a permanent thick dielectric layer that is patterned
underneath specific locations to create the desired 3-D interconnect shape. A 3-D seed layer
is deposited above the SU-8 and the substrate to ensure 3-D electroplating current flow. The …
This paper presents a new and efficient low-cost multilayer 3-D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multilevel 3-D interconnects in a single metallization step. The SU-8 is used as a permanent thick dielectric layer that is patterned underneath specific locations to create the desired 3-D interconnect shape. A 3-D seed layer is deposited above the SU-8 and the substrate to ensure 3-D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized 3-D copper electroplating process is later used to grow 3-D interconnects, ensuring transition between all metallic layers. Finally, high-Q (55 at 5 GHz) power inductors are designed and integrated above a 50 W RF power laterally diffused metal oxide semiconductor device using this process.
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