3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs

Z Shirmohammadi, HZ Sabzi… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
2017 IEEE International High Level Design Validation and Test …, 2017ieeexplore.ieee.org
One of the cost-efficient fabrication approaches for connecting layers in three-dimensional
integrated circuits (3D ICs) is the use of through-silicon vias (TSVs). However, the large and
closely spaced nature of TSVs has made them seriously prone to coupling capacitances
between TSVs, increasing the probability of crosstalk faults. To reduce crosstalk faults in 3D
ICs, this paper proposes a dynamic numerical-based crosstalk avoidance mechanism called
3D-DyCAC. The 3D-DyCAC mechanism is applied in two phases. In the first phase, a …
One of the cost-efficient fabrication approaches for connecting layers in three-dimensional integrated circuits (3D ICs) is the use of through-silicon vias (TSVs). However, the large and closely spaced nature of TSVs has made them seriously prone to coupling capacitances between TSVs, increasing the probability of crosstalk faults. To reduce crosstalk faults in 3D ICs, this paper proposes a dynamic numerical-based crosstalk avoidance mechanism called 3D-DyCAC. The 3D-DyCAC mechanism is applied in two phases. In the first phase, a numerical system-based crosstalk avoidance code (CAC) is proposed to reduce the opposite-direction transitions in adjacent TSVs. This numerical-based CAC generates code words with cumulative groups of 1s and 0s to minimize adjacent transitions in arranged N × N meshes of TSVs. The proposed CAC has no ambiguity in representing code words and generates a unique code word for each data word. In the second phase, a triangular window (TW) is introduced to consider overlaps between the cells of TSVs during the arrangement of code words on TSVs. In the TW area, the content of the victim TSV and/or the content of adjacent bit positions can be dynamically inverted based on the content of data words. Evaluation results show that 3D-DyCAC reduces the area occupation, power consumption, and power-delay product of codec by 10%, 24%, and 46%, respectively, in comparison with state-of-the-art mechanism 3DLAT.
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