A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver
R Farjad-Rad, CKK Yang… - IEEE Journal of Solid …, 2000 - ieeexplore.ieee.org
IEEE Journal of Solid-State Circuits, 2000•ieeexplore.ieee.org
An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit
preshaping in combination with receive equalization to reduce intersymbol interference due
to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and
demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel
frequency acquisition scheme and a linear phase-locked loop that achieves a loop
bandwidth of 35 MHz, phase margin of 50/spl deg/, and capture range of 20 MHz without a …
preshaping in combination with receive equalization to reduce intersymbol interference due
to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and
demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel
frequency acquisition scheme and a linear phase-locked loop that achieves a loop
bandwidth of 35 MHz, phase margin of 50/spl deg/, and capture range of 20 MHz without a …
An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50/spl deg/, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2/spl times/2 mm/sup 2/ chip consumes 1.1 W at 8 Gb/s with a 3-V supply.
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