A 1.4 Gb/s DLL using 2nd order charge-pump scheme for low phase/duty error for high-speed DRAM application
K hyoun Kim, JB Lee, WJ Lee… - Digest of Technical …, 2003 - inha.elsevierpure.com
A technique for reducing phase error of DLL/PLL due to non-ideal characteristics of the
charge pump is proposed, it makes the output of the charge pump virtually grounded to
eliminate the current mismatch and to seamlessly convert the locking information into digital
form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with the
speed of 1.4 Gb/s.
charge pump is proposed, it makes the output of the charge pump virtually grounded to
eliminate the current mismatch and to seamlessly convert the locking information into digital
form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with the
speed of 1.4 Gb/s.
A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application
K Kim, JB Lee, WJ Lee, BH Jeong… - … Solid-State Circuits …, 2004 - ieeexplore.ieee.org
A technique for reducing the phase error of DLL/PLLs, due to non-ideal characteristics of the
charge pump, is proposed. It makes the output of the charge pump virtually grounded, to
eliminate the current mismatch and to seamlessly convert the locking information into digital
form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with a
speed of 1.4 Gb/s.
charge pump, is proposed. It makes the output of the charge pump virtually grounded, to
eliminate the current mismatch and to seamlessly convert the locking information into digital
form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with a
speed of 1.4 Gb/s.
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