A 112Gb/S 2.6 pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
C Menolfi, M Braendli, PA Francese… - … Solid-State Circuits …, 2018 - ieeexplore.ieee.org
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 2018•ieeexplore.ieee.org
The ongoing demand for higher data rates in wireline and optical communications has led to
emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the
definition phase they will rely on multi-level signaling such as PAM-4 along with an
increasing amount of digital signal processing. In the foreseeable future, a high-performance
TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,
3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 …
emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the
definition phase they will rely on multi-level signaling such as PAM-4 along with an
increasing amount of digital signal processing. In the foreseeable future, a high-performance
TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,
3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 …
The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In the foreseeable future, a high-performance TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 SST Tx that is based on a quarter-rate 56GS/s 8b SST DAC along with a digital 8-tap FIR filter for channel equalization.
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