A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm
B Erbagci, NEC Akkaya… - 2015 IEEE Custom …, 2015 - ieeexplore.ieee.org
2015 IEEE Custom Integrated Circuits Conference (CICC), 2015•ieeexplore.ieee.org
The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly
contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-
Box implementations, we use full-custom 256× 8-bit ROMs, which significantly improve
performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption
accelerator using ROM-based S-Boxes in 65nm bulk CMOS which operates at 2.2 GHz and
consumes 523mW at 1.0 V, 27° C. In counter-mode operation (CTR), the throughput is 275.2 …
contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-
Box implementations, we use full-custom 256× 8-bit ROMs, which significantly improve
performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption
accelerator using ROM-based S-Boxes in 65nm bulk CMOS which operates at 2.2 GHz and
consumes 523mW at 1.0 V, 27° C. In counter-mode operation (CTR), the throughput is 275.2 …
The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256×8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk CMOS which operates at 2.2GHz and consumes 523mW at 1.0V, 27°C. In counter-mode operation (CTR), the throughput is 275.2Gbps, which is 5.2x higher than the highest ever reported in the literature to our knowledge.
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