… technologies that limit MEMS integration into SoCs. This work demonstrates a charge pump
design in 65nm technology … The pump achieves 34V output by using three different charge …

… voltage ranges of conventional CP designs in a 65-nm CMOS technology are limited to 12 V
and −12 V… The pump maintains >34 V output voltages for Iload < 10 μA at Vdd = 2.75 V. The …

… In [15], a charge pump that can generate an output voltage of 14.8 V from a 1.8 V … charge
pump fabricated in a 0.13-μm CMOS technology from GlobalFoundries (formerly IBM technology…

… on CMOS device is designed. The objective of this article is to achieve a 20V output using
charge pump from a … reduction for digital intensive circuit in advanced nano CMOS technology. …

… ,34 to eliminate the reversion loss. To properly control the N-switches MNa and MNb, a charge
pump-… KK Yang, “A 34V charge pump in 65nm bulk CMOS technology,” IEEE ISSCC Dig. …

… architecture demonstrates maximum efficiency of 34% in high-… purpose 0.18 μm CMOS
technology and occupies a total area … charge pump and as a 1-stage charge pump. For 1-stage …

… , S.; Yang, CK A 34V charge pump in 65nm bulk CMOS technology. In Proceedings of the
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), …

… The proposed charge pump system for SPAD biasing was implemented in a general purpose
0.13 μm bulk CMOS technology (Global Foundries 8RF). … KK Yang, “A 34V charge pump …

… In this design, we implemented 12 charge pump stages as a compromise between recovery
time and charge pump efficiency. A pumping frequency of 100 MHz achieves <200 ns …

… Cacciatori, and ZM Kovacs-Vajna, “Charge pump architectures based on dynamic gate
control of the pass-transistors,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. …