A 43-nW 10-bit 1-kS/s SAR ADC in 180nm CMOS for biomedical applications
2015 IEEE Asia Pacific Conference on Postgraduate Research in …, 2015•ieeexplore.ieee.org
This work presents an ultra-low power 10-bit, 1-KS/s successive approximation register
(SAR) analog-to-digital converter (ADC) for biomedical applications. To achieve the nano-
watt range power consumption, an ultra-low-power design technique has been utilized,
inflicting maximum simplicity on the ADC architecture and low transistor count. ADC was
designed in 180nm CMOS technology with a 1-V power supply and a 1-kS/s sampling rate
for monitoring bio potential signals. The ADC achieves a signal-to-noise plus distortion ratio …
(SAR) analog-to-digital converter (ADC) for biomedical applications. To achieve the nano-
watt range power consumption, an ultra-low-power design technique has been utilized,
inflicting maximum simplicity on the ADC architecture and low transistor count. ADC was
designed in 180nm CMOS technology with a 1-V power supply and a 1-kS/s sampling rate
for monitoring bio potential signals. The ADC achieves a signal-to-noise plus distortion ratio …
This work presents an ultra-low power 10-bit, 1-KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. To achieve the nano-watt range power consumption, an ultra-low-power design technique has been utilized, inflicting maximum simplicity on the ADC architecture and low transistor count. ADC was designed in 180nm CMOS technology with a 1-V power supply and a 1-kS/s sampling rate for monitoring bio potential signals. The ADC achieves a signal-to-noise plus distortion ratio of 57.16 dB and consumes 43 nW, resulting in a figure of merit of 73 fJ/conversion-step.
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