… A 4.5M DRAM that interfaces to the bus directly and provides a 500-megabyte/s data rate
has been developed. … This paper describes a 4.5M DRAM that directly interfaces to the …

… This paper describes a 2.5-V, 72-Mbit DRAM based on packet protocol with a 16–bank …
, MM Griffin, M. Horowitz, TH Lee, and V. Lee, “A 500 Megabyte/s datarate 4.5 M DRAM,” …

… Our solution for attaining a higher data rate is to increase the DRAM core’s intrinsic
operating speed without employing a data-multiplexing technique. We propose two schemes to …

… Abstract–This paper describes a silicon on insulator (SOI) DRAM which has a body bias …
scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-…

… kb*9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was
achieved by designing a DRAM core … The DRAM has a 1-kbyte*2-line sense-amp cache and is …

… -density CMOS DRAM's such as 16 M DRAM and 256 M DRAM. I Jai-Hoon Sim (S'92-M'93) …
for the development of DRAM's such as 1 Mb DRAM, 4 Mb DRAM, 16 Mb DRAM, and 1 Gb …

… , and the DRAM chip is equipped … DRAM chip, and the DRAM chip stores the encoded bus
data and the flag information without the decode processing. In the read operation, the DRAM …

… A 512-Mb test device is fabricated using a 0.13- m DRAM process … Therefore, as the data
rate increases, the influence of the … 3(b) shows the relationship between the maximum data rate …

… be a bottleneck in increasing the data rate. In this work, an equalization scheme was applied
to the chip-to-chip communication between a DRAM controller and DRAMs. We used a sort …

… in a bus interface at a data rate of 200 MHz. A test … DRAM’s are connected to a bus line.
Therefore, signal reflections occur at the stubs of the bus or at the parasitic elements of DRAM …