A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V microprocessor using scalable dynamic leakage-suppression logic
IEEE Solid-State Circuits Letters, 2019•ieeexplore.ieee.org
This letter presents an RISC-V microprocessor implemented using a proposed scalable
dynamic leakage suppression (SDLS) logic style. Together with a custom adaptive clock
generator and voltage scaling controller, the SDLS RISC-V microprocessor realizes a fully
integrated modified dynamic voltage and frequency scaling (DVFS) scheme that enables nW-
level performance flexibility for battery-less IoT sensing nodes in energy-scarce
environments. At the nominal core VDD of 0.6 V, the core can scale its performance from 6 …
dynamic leakage suppression (SDLS) logic style. Together with a custom adaptive clock
generator and voltage scaling controller, the SDLS RISC-V microprocessor realizes a fully
integrated modified dynamic voltage and frequency scaling (DVFS) scheme that enables nW-
level performance flexibility for battery-less IoT sensing nodes in energy-scarce
environments. At the nominal core VDD of 0.6 V, the core can scale its performance from 6 …
This letter presents an RISC-V microprocessor implemented using a proposed scalable dynamic leakage suppression (SDLS) logic style. Together with a custom adaptive clock generator and voltage scaling controller, the SDLS RISC-V microprocessor realizes a fully integrated modified dynamic voltage and frequency scaling (DVFS) scheme that enables nW-level performance flexibility for battery-less IoT sensing nodes in energy-scarce environments. At the nominal core VDD of 0.6 V, the core can scale its performance from 6 nW at 11-Hz operating frequency to 140 nW at 8.2-kHz operating frequency. Across the supply voltage range, the core is capable of delivering minimum power of 840 pW, maximum frequency of 41.5 kHz, and a minimum energy of 13.4 pJ/cycle.
ieeexplore.ieee.org