This paper presents a multiplier circuit using balanced ternary (BT) notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in designing a fast multiplier circuit. The circuit is implemented with recharged semi-floating gate (RSFG) devices. The circuit operates at 1 GHz clock frequency at a supply voltage of only 1.0 Volt. The circuit is simulated by using CadenceregAnalog Design Environment, with CMOS090 process parameters, a 90nm general purpose bulk CMOS process from STMicroelectronics with 7 metal layers