The work presents a new principle for microprocessor design based on a pairwise-balanced
combinatorial arrangement of processing and memory elements. The proposed apparatus
uses two operand instructions so that a set of executable machine instructions is partitioned
by these address pairs. This partitioning allows concurrent processing of data-independent
instructions. Because the partitioning is done at compile-time, this design extracts
substantial instruction-level parallelism from executable code without the overhead of run …